EPM7064LC68-12N

programmable logic device, 25 mA, 7.0 V, PLCC68

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PartNumber:: EPM7064LC68-12N

Brand:: Altera Corporation - ALTR | Pack: PLCC | D/C: 09+

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Products Upload time: 2012-07-25

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Part Number:EPM7064LC68-12N
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Product Summary

The EPM7064LC68-12N is a programmable logic device. The EPM7064LC68-12N of high density, high performance PLDs is based on Altera’s second generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM based The EPM7064LC68-12N provides 600 to 5,000 usable gates, ISP, pin to pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the －5, －6, －7, and －10 speed grades as well as MAX 7000 and MAX 7000E devices in －5, －6, －7,－10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.

Parametrics

absolute maximum ratings: (1)IOUT DC output current, per pin: –25, 25 mA; (2)TSTG Storage temperature No bias: –65, 150℃; (3)TAMB Ambient temperature Under bias: –65, 135 ℃; (4)VCC Supply voltage With respect to ground (2): –2.0, 7.0 V; (5)VI DC input voltage With respect to ground (2): –2.0, 7.0 V.

Features

EPM7064LC68-12N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs)based on second-generation MAX® architecture; (2)5.0 V in system programmability (ISP)through the built in IEEE Std. 1149.1 Joint Test Action Group (JTAG)interface available in MAX 7000S devices ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0 V MAX 7000 devices and 5.0 V ISP based MAX 7000S devices; (4)Built in JTAG boundary scan test (BST)circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5ns pin to pin logic delays with up to 175.4 MHz counter frequencies (including interconnect); (7)PCI compliant devices available.