LPC2106B

Product Summary

The LPC2106B is a single-chip 32-bit microcontroller. The LPC2106B is based on a 16/32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 128 kbytes (kB) of embedded high speed flash memory. A 128 bit wide memory interface and a unique accelerator architecture enable 32 bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty. Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale.The LPC2106B is with a wide range of serial communications interfaces and on-chip SRAM options up to 64 kilobytes, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32 bit timers, PWM channels and 32 GPIO lines make these microcontrollers particularly suitable for industrial control and medical systems.

Parametrics

LPC2106B absolute maximum ratings: (1)VDD1.8 Supply voltage: 1.65, 1.8, 1.95 V; (2)VDD3 External rail supply voltage: 3.0, 3.3, 3.6 V; (3)IIL LOW level input current, no pull-up Vi = 0: 3 mA; (4)IIH HIGH level input current, no pull down Vi = VDD3: 3 mA; (5)IOZ 3-state output leakage, no pull-up/down Vo = 0, Vo = VDD3: 3 mA; (6)Vo Output voltage, output active: 0,VDD3 V; (7)VIH HIGH level input voltage: 2.0 V; (8)VIL LOW level input voltage: 0.8 V; (9)Vhys Hysteresis voltage: 0.4 V.

Features

LPC2106B features: (1)16/32 bit ARM7TDMI-S processor; (2)16/32/64 kB o -chip Static RAM; (3)128 kB o -chip Flash Program Memory. 128 bit wide i terface/accelerator e ables high speed 60 MHz operatio; (4)I -System Programmi g (ISP)a d I -Applicatio Programmi g (IAP)via o -chip boot-loader software. Flash programmi g takes 1 ms per 512 byte li e. Si gle sector or full chip erase takes 400 ms; (5)Vectored I terrupt Co troller with co figurable priorities a d vector addresses; (6)EmbeddedICE-RT i terface e ables breakpoi ts a d watchpoi ts. I terrupt service routi es ca co ti ue to execute whilst the foregrou d task is debugged with the o -chip RealMo itor software; (7)Embedded Trace Macrocell e ables o -i trusive high speed real-time traci g of i structio executio; (8)Multiple serial i terfaces i cludi g two UARTs (16C550), Fast I2C (400 kbits/s)a d SPI; (9)Two 32-bit timers (7 capture/compare cha els), PWM u it (6 outputs), Real Time Clock a d Watchdog; (10)Up to thirty-two 5 V tolera t ge eral purpose I/O pi s i a ti y LQFP48 (7×7 mm2)package.

Diagrams