PEEL18CV8P-25L

Product Summary

The PEEL18CV8P-25L is a Programmable Electrically Erasable Logic device providing an attractive alternative to ordinary PLDs. The PEEL18CV8P-25L offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL18CV8P-25L architecture allows it to replace over 20 standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides additional architecture features so more logic can be put into every design. Anachip’s JEDEC file translator instantly converts to the PEEL18CV8P-25L existing 20-pin PLDs without the need to rework the existing design. Development and programming support for the PEEL18CV8P-25L is provided by popular third-party program- mers and development software.

Parametrics

PEEL18CV8P-25L absolute maximum ratings: (1)vcc Supply Voltage Relative to Ground: －0.5 to + 6.0V; (2)VI，VO Voltage Applied to Any Pin" Relative to Ground1: -0.5 to VCC + 0.6V; (3)10 Output Current Per Pin (IOL, IOH): ±25mA; (4)TST Storage Temperature: -65 to+ 150°C; (5)TLT Lead Temperature Soldering 10 Seconds: +300°C.

Features

PEEL18CV8P-25L features: (1)Multiple Speed Power, Temperature Options: VCC = 5 Volts ±10%, Speeds ranging from 7ns to 25 ns, Power as low as 37mA at 25MHz, Commercial and industrial versions available; (2)CMOS Electrically Erasable Technology: Superior factory testing, Reprogrammable in plastic package, Reduces retrofit and development costs; (3)Development / Programmer Support: Third party software and programmers, WinPLACE Development Software, PLD-to-PEELTM JEDEC file translator; (4)Architectural Flexibility: Enhanced architecture fits in more logic, 74 product terms x 36 input AND array, 10 inputs and 8 I/O pins, 12 possible macrocell configurations, Asynchronous clear, Independent output enables, 20 Pin DIP/SOIC/TSSOP and PLCC; (5)Application Versatility: Replaces random logic, Super sets PLDs (PAL, GAL, EPLD), Enhanced Architecture fits more logic than ordinary PLDs.

Diagrams