CD4001BD

NOR gate, 14-lead, hermetic dual-in-line ceramic package

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Price:: US $1.00~2.00 / piece [Get Latest Price]

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	US $1.00~2.00

PartNumber:: CD4001BD

Brand:: Analog Devices - ADI | Pack: DIP | D/C: 03+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-08-02

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Part Number:CD4001BD
US $1.00 - 2.00
A50L-0001-0175

US $100.00 - 100.00 / Piece
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HEF4051BT

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Product Summary

The CD4001BD NOR gate provides the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. It is supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Parametrics

Absolute maximum ratings: (1)DC Supply Voltage Range, (VDD)(Voltage Referenced to VSS Terminals): -0.5V to +20V; (2)Input Voltage Range, All Inputs: -0.5V to VDD +0.5V; (3)DC Input Current, Any One Input: ±10mA; (4)Operating Temperature Range: -55℃ to +125℃; (5)power dissipation per package(PD): 500mw for TA=-55℃ to 100℃; derate linearity at 12mw/ to 200mw for TA=-100℃ to 125℃; (6)device dissipation per output transistor for TA=full package-temperature range: 100mw ; (7)Storage Temperature Range (TSTG): -65℃ to +150℃; (8)Lead Temperature (During Soldering) At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum: +265℃.

Features

Features: (1)Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V; (2)Buffered Inputs and Outputs; (3)Standard Symmetrical Output Characteristics; (4)100% Tested for Maximum Quiescent Current at 20V; (5)5V, 10V and 15V Parametric Ratings; (6)Maximum Input Current of 1μA at 18V Over Full Package-Temperature Range; 100nA at 18V and +25℃; (7)Noise Margin (Over Full Package Temperature Range): 1V at VDD = 5V; 2V at VDD = 10V; 2.5V at VDD = 15V; (8)Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device.