(China (Mainland))
Product Summary
The ISPL1032-60LJ is a high-density programmable logic device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ISPL1032-60LJ features 5V in-system programmability and in-system diagnostic capabilities. The ISPL1032-60LJ offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ISPL1032-60LJ device adds two new global output enable pins and two additional dedicated inputs.
Parametrics
ISPL1032-60LJ absolute maximum ratings: (1)Supply Voltage Vcc: -0.5 to +7.0V; (2)Input Voltage Applied: -2.5 to VCC +1.0V; (3)Off-State Output Voltage Applied: -2.5 to VCC +1.0V; (4)Storage Temperature: -65 to 150 °C; (5)Case Temp. with Power Applied: -55 to 125 °C; (6)Max. Junction Temp. (TJ) with Power Applied: 150°C
Features
ISPL1032-60LJ features: (1) IN-SYSTEM PROGRAMMABLE: In-System Programmable 5V Only, Increased Manufacturing Yields, Reduced Time-to-; (2)Market and Improved Product Quality, Reprogram Soldered Devices for Faster Prototyping, ; (3) OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS: Complete Programmable Device Can Combine Glue Logic and Structured Designs, Enhanced Pin Locking Capability, Four Dedicated Clock Input Pins, Synchronous and Asynchronous Clocks, Programmable Output Slew Rate Control to Minimize Switching Noise, Flexible Pin Placement, Optimized Global Routing Pool Provides Global Interconnectivity.
Diagrams
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ispLSI 1016-60LJ |
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CPLD - Complex Programmable Logic Devices USE ispMACH 4000V |
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ispLSI 1016-60LJI |
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ispLSI 1016-60LT44 |
Lattice |
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V |
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