(China (Mainland))
Product Summary
The LCX112 is a dual J-K flip-flop. Each flip-flop has independent
J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accomplished
by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technology
to achieve high speed operation while maintaining
CMOS low power dissipation
Features
■ 5V tolerant inputs
■ 2.3V–3.6V VCC specifications provided
■ 7.5 ns tPD max (VCC = 3.3V), 10 μA ICC max
■ Power down high impedance inputs and outputs
■ ±24 mA output drive (VCC = 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model > 2000V
Machine model > 2000V
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 |
 74LCX112M |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
|
|
||||||||||||
|
74LCX112M_Q |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
Negotiable |
|
||||||||||||
|
74LCX112MX |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
|
|
||||||||||||
 |
74LCX112MTCX |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
|
|
||||||||||||
|
74LCX112MTC |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
|
|
||||||||||||
 |
74LCX112MTC_Q |
Fairchild Semiconductor |
Flip Flops J-K Neg Flip-Flop |
Data Sheet |
Negotiable |
|
||||||||||||
